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PIC18F66K80 FAMILY

DS39977F-page 108

2010-2012 Microchip Technology Inc.

6.3

Data Memory Organization

The data memory in PIC18 devices is implemented as

static RAM. Each register in the data memory has a

12-bit address, allowing up to 4,096 bytes of data

memory. The memory space is divided into 16 banks

that contain 256 bytes each.

Figure 6-6 and Figure 6-7 show the data memory

organization for the devices.

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratchpad operations in the user’s

application. Any read of an unimplemented location will

read as ‘0’s.

The instruction set and architecture allow operations

across all banks. The entire data memory may be

accessed by Direct, Indirect or Indexed Addressing

modes. Addressing modes are discussed later in this

section.

To ensure that commonly used registers (select SFRs

and select GPRs) can be accessed in a single cycle,

PIC18 devices implement an Access Bank. This is a

256-byte memory space that provides fast access to

select SFRs and the lower portion of GPR Bank 0 with-

out using the Bank Select Register. For details on the

Access RAM, see Section 6.3.2 “Access Bank”.

6.3.1

BANK SELECT REGISTER

Large areas of data memory require an efficient

addressing scheme to make rapid access to any

address possible. Ideally, this means that an entire

address does not need to be provided for each read or

write operation. For PIC18 devices, this is accom-

plished with a RAM banking scheme. This divides the

memory space into 16 contiguous banks of 256 bytes.

Depending on the instruction, each location can be

addressed directly by its full 12-bit address, or an

eight-bit, low-order address and a four-bit Bank Pointer.

Most instructions in the PIC18 instruction set make use

of the Bank Pointer, known as the Bank Select Register

(BSR). This SFR holds the four Most Significant bits of

a location’s address. The instruction itself includes the

eight Least Significant bits. Only the four lower bits of

the BSR are implemented (BSR<3:0>). The upper four

bits are unused and always read as ‘0’, and cannot be

written to. The BSR can be loaded directly by using the

MOVLB

instruction.

The value of the BSR indicates the bank in data

memory. The eight bits in the instruction show the loca-

tion in the bank and can be thought of as an offset from

the bank’s lower boundary. The relationship between

the BSR’s value and the bank division in data memory

is shown in Figure 6-7.

Since up to 16 registers may share the same low-order

address, the user must always be careful to ensure that

the proper bank is selected before performing a data

read or write. For example, writing what should be

program data to an eight-bit address of F9h while the

BSR is 0Fh, will end up resetting the Program Counter.

While any bank can be selected, only those banks that

are actually implemented can be read or written to.

Writes to unimplemented banks are ignored, while

reads from unimplemented banks will return ‘0’s. Even

so, the STATUS register will still be affected as if the

operation was successful. The data memory map in

Figure 6-6 indicates which banks are implemented.

In the core PIC18 instruction set, only the MOVFF

instruction fully specifies the 12-bit address of the

source and target registers. When this instruction

executes, it ignores the BSR completely. All other

instructions include only the low-order address as an

operand and must use either the BSR or the Access

Bank to locate their target registers.

Note:

The operation of some aspects of data

memory are changed when the PIC18

extended instruction set is enabled. See

Section 6.6 “Data Memory and the

Extended Instruction Set”

for more

information.

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